Index of /HEAD/ports/cad

[ICO]NameLast modifiedSize

[PARENTDIR]Parent Directory  -
[   ]Makefile2019-08-13 06:52 2.5K
[DIR]NASTRAN-95/2019-07-27 06:53 -
[DIR]abc/2019-04-10 01:13 -
[DIR]admesh/2018-07-16 01:13 -
[DIR]adms/2017-04-23 00:55 -
[DIR]alliance/2019-09-16 06:52 -
[DIR]astk-client/2014-03-19 07:11 -
[DIR]astk-serveur/2019-02-20 01:14 -
[DIR]atlc/2016-01-13 06:51 -
[DIR]basicdsp/2019-07-27 06:53 -
[DIR]brickutils/2019-09-09 01:16 -
[DIR]calculix-ccx/2019-07-27 06:53 -
[DIR]calculix/2019-07-27 06:53 -
[DIR]cascade/2017-05-30 01:14 -
[DIR]chipvault/2014-01-23 03:36 -
[DIR]cura-engine/2019-07-27 06:53 -
[DIR]digital/2019-07-23 06:52 -
[DIR]dinotrace/2019-08-14 06:52 -
[DIR]dxf2fig/2019-09-16 06:52 -
[DIR]electric-ng/2018-08-16 06:52 -
[DIR]electric/2017-11-10 01:02 -
[DIR]feappv/2019-07-27 06:53 -
[DIR]fidocadj/2016-05-20 01:11 -
[DIR]freecad/2019-08-20 06:52 -
[DIR]freehdl/2019-07-27 06:53 -
[DIR]fritzing/2019-08-20 06:52 -
[DIR]gdsreader/2014-08-31 05:07 -
[DIR]gdt/2017-01-21 06:51 -
[DIR]geda/2019-09-19 01:16 -
[DIR]gerbv/2019-09-16 06:52 -
[DIR]ghdl/2019-09-16 06:52 -
[DIR]gmsh/2019-07-27 06:53 -
[DIR]gnucap/2018-10-28 01:16 -
[DIR]gplcver/2019-06-20 01:16 -
[DIR]gspiceui/2019-07-27 06:53 -
[DIR]gtkwave/2019-07-27 06:53 -
[DIR]impact/2016-12-09 06:51 -
[DIR]irsim/2018-06-27 01:19 -
[DIR]iverilog/2019-08-19 01:10 -
[DIR]jspice3/2019-05-13 01:18 -
[DIR]k40-whisperer/2019-09-11 01:17 -
[DIR]kicad-devel/2019-08-20 06:52 -
[DIR]kicad-doc/2019-08-12 01:14 -
[DIR]kicad-library-footprints-devel/2019-07-27 06:53 -
[DIR]kicad-library-footprints/2019-08-12 01:15 -
[DIR]kicad-library-packages3d-devel/2019-07-27 06:53 -
[DIR]kicad-library-packages3d/2019-08-12 01:14 -
[DIR]kicad-library-symbols-devel/2019-07-27 06:53 -
[DIR]kicad-library-symbols/2019-08-12 01:15 -
[DIR]kicad-library-templates-devel/2019-07-27 06:53 -
[DIR]kicad-library-templates/2019-08-12 01:15 -
[DIR]kicad/2019-08-20 06:52 -
[DIR]klayout/2019-07-27 06:53 -
[DIR]ldraw/2019-09-06 01:17 -
[DIR]leocad/2019-09-06 01:17 -
[DIR]lepton-eda/2019-08-06 01:16 -
[DIR]libopencad/2019-07-27 06:53 -
[DIR]librecad/2019-08-20 06:52 -
[DIR]libredwg/2019-07-12 01:18 -
[DIR]linux-eagle5/2018-05-08 01:12 -
[DIR]linuxcnc-devel/2019-08-20 06:52 -
[DIR]logisim/2014-12-21 05:03 -
[DIR]magic/2017-05-24 01:14 -
[DIR]meshdev/2016-05-20 01:11 -
[DIR]netgen/2019-08-08 01:15 -
[DIR]ngspice_rework/2019-08-12 01:14 -
[DIR]opencascade/2019-08-08 01:14 -
[DIR]openscad-devel/2019-09-07 01:19 -
[DIR]openscad/2019-08-20 06:52 -
[DIR]openvsp/2019-09-05 06:52 -
[DIR]p5-GDS2/2018-05-28 06:54 -
[DIR]p5-Verilog-Perl/2017-10-13 01:21 -
[DIR]pcb/2019-03-17 01:15 -
[DIR]pdnmesh/2019-07-27 06:53 -
[DIR]py-gdspy/2019-07-27 06:53 -
[DIR]py-lcapy/2019-07-27 06:53 -
[DIR]py-phidl/2019-07-27 06:53 -
[DIR]py-pycam/2019-07-27 06:53 -
[DIR]py-pyfda/2019-07-27 06:53 -
[DIR]python-gdsii/2019-02-01 01:17 -
[DIR]pythoncad/2018-06-21 06:53 -
[DIR]qcad/2019-09-19 01:16 -
[DIR]qelectrotech/2019-09-05 01:13 -
[DIR]qmls/2014-01-23 03:35 -
[DIR]repsnapper/2019-07-27 06:53 -
[DIR]rubygem-gdsii/2016-05-17 06:50 -
[DIR]scotch/2019-07-27 06:53 -
[DIR]solvespace/2019-07-27 06:53 -
[DIR]sp2sp/2019-05-04 06:52 -
[DIR]spice/2016-11-12 01:06 -
[DIR]stepcode/2019-07-27 06:53 -
[DIR]sumo/2019-06-28 01:14 -
[DIR]sweethome3d/2018-03-27 06:52 -
[DIR]tkgate/2019-08-10 01:15 -
[DIR]tochnog/2019-07-27 06:53 -
[DIR]transcalc/2016-12-09 06:51 -
[DIR]varkon/2017-05-24 01:14 -
[DIR]verilator/2019-07-27 06:53 -
[DIR]verilog-mode.el/2019-08-14 06:52 -
[DIR]xcircuit/2019-09-10 01:17 -
[DIR]z88/2019-08-14 06:52 -
[DIR]zcad/2019-09-04 06:52 -